1. Field of the Invention
The invention relates to Field Programmable Gate Arrays (FPGAs). More particularly, the invention relates to input/output (I/O) voltage levels in an FPGA.
2. Description of the Background Art
Existing I/O structures for integrated circuits (ICs) are typically designed to function according to a specific I/O standard. There are several different I/O standards in use, and new standards are often introduced. These I/O standards typically include such factors as output drive strength, receiver type, output driver type, and output signal slew rate. One such I/O standard is the GTL+ standard, described in pages 46 through 50 of the Pentium Pro Processor data sheet entitled xe2x80x9cPENTIUM PRO PROCESSOR AT 150 MHz, 166 MHz, 180 MHz and 200 Mhzxe2x80x9d, published November 1995 and available from Intel Corporation, 2200 Mission College Blvd., Santa Clara, Calif. 95052-8119, which are incorporated herein by reference. (xe2x80x9cPentiumxe2x80x9d is a registered trademark owned by Intel Corporation.)
A typical Input/Output Block (IOB) in an FPGA supports only one I/O standard. However, FPGAs are often used to implement xe2x80x9cglue logicxe2x80x9d (logic used to interface between two or more standard circuits) and therefore often interface with multiple ICs. It would be desirable for an FPGA to be able to interface with ICs that follow two or more different I/O standards.
Additionally, existing I/O structures are typically designed to function at a specific supply voltage. For example, for many years, the majority of commercially available ICs were designed to function at a supply voltage of 5 Volts. However, as the typical gate length decreases throughout the IC industry, the typical supply voltage used in FPGAs and other ICs is decreasing. Many ICs are now available that function at 3.3 Volts, and voltages of 2.5 Volts and below are commonly discussed. Therefore, it would be desirable for an FPGA to be able to interface with different ICs that function at two or more different supply voltages.
It is known in FPGA design to use one voltage for driving outputs and a different voltage in the interior (core) of the FPGA. One FPGA having a separate output voltage supply is the FLEX 10K(trademark) FPGA from Altera Corporation, as disclosed on pages 54 to 59 of the xe2x80x9cFLEX 10K Embedded Programmable Logic Family Data Sheetxe2x80x9d from the Altera Digital Library 1996, available from Altera Corporation, 2610 Orchard Parkway, San Jose, Calif. 95134-2020, which are incorporated herein by reference. (xe2x80x9cFLEX 10Kxe2x80x9d is a trademark of Altera Corporation.) In the FLEX 10K device, output voltage supply pins are provided that can be connected as a group to only one output supply voltage, either a 3.3-Volt or a 5-Volt power supply. Known FPGAs therefore typically provide for a single output supply voltage, which applies to all configurable I/O buffers on the FPGA.
Output slew rate is also programmable in known FPGAs including the XC3000 family of devices from Xilinx, Inc., as described on pages 4-292 through 4-293 of the Xilinx 1996 Data Book entitled xe2x80x9cThe Programmable Logic Data Bookxe2x80x9d, available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, which are incorporated herein by reference. (Xilinx, Inc., owner of the copyright, has no objection to copying these and other pages referenced herein but otherwise reserves all copyright rights whatsoever.) However, in such FPGAs, factors such as output drive strength, receiver type, and output driver type are not known to be configurable to meet a particular I/O standard.
Some I/O standards require that an input reference voltage be supplied. An input voltage above the input reference voltage is interpreted as a xe2x80x9chighxe2x80x9d voltage level; an input voltage below the input reference voltage is interpreted as a xe2x80x9clowxe2x80x9d voltage level. Therefore, the input reference voltage establishes a xe2x80x9ctrip pointxe2x80x9d for interpreting input signals. As far as is known, no FPGA allows a user to supply an input reference voltage.
To fully understand the invention, it is first necessary to define the several voltage levels involved in input/output buffers according to the several aspects of the invention. The xe2x80x9ccore voltagexe2x80x9d, VCCC, is the supply voltage used for the interior (non-I/O) part of the FPGA. (In one embodiment, VCCC is also used as the supply voltage for the pulldown logic in the pre-driver and output buffer.) The xe2x80x9cinput supply voltagexe2x80x9d, VCCI, is the supply voltage used for the input buffer. The xe2x80x9coutput supply voltagexe2x80x9d, VCCO, is the supply voltage used for the pullup logic in the output buffer. The terms VCCC, VCCI, and VCCO are also used to designate the power supplies supplying the corresponding voltages. Two or more of these voltages may be connected to each other; in one embodiment VCCC and VCCI are connected together and VCCO is separate. The input reference voltage required by some I/O standards is referenced herein as VREF.
A first aspect of the invention comprises a configurable input/output buffer for an FPGA that can be configured to comply with any of two or more different I/O standards. In one embodiment of the invention, input signals can be supplied to the FPGA at a voltage level with a specified switching point, where the specified switching point (the input reference voltage) is externally supplied to the FPGA. Other factors that vary from one I/O standard to another are also configurable.
One input/output buffer according to the invention comprises two configurable buffers, an input buffer and an output buffer. The two buffers may be separately or collectively configurable. In some embodiments, only the input buffer, or only the output buffer, is configurable.
In one embodiment, the input buffer can be configured to select a particular I/O standard. The input standard is selected by configuring an input multiplexer that selects between three input paths from the pad to an input signal line: 1) a Schmitt trigger such as is commonly used in FPGAs; 2) a differential amplifier for low input reference voltages (voltages below about 0.7 Volts); and 3) a differential amplifier for high input reference voltages (voltages above about 0.7 Volts). A standard input buffer can be used instead of a Schmitt trigger. The input reference voltage for the differential amplifier is dependent on the I/O standard and is supplied by the user. In one embodiment, two or more differential amplifiers in the same configurable input buffer use different input reference voltages.
In one embodiment, the output buffer can be configured to select a particular I/O standard. The I/O standard is selected by providing a series of pullups (pullup devices) and pulldowns (pulldown devices) on the output pad line (a signal line connected to the I/O pad), and by connecting the appropriate supply voltage to the output supply voltage (VCCO) pads. One or more pullups and pulldowns are enabled or disabled by configuration logic, such that the resulting total pullup and pulldown transistor widths correspond to the values needed to implement a particular I/O standard. According to the invention, for any particular standard the maximum voltage on a voltage-high output signal is set by the user by connecting the output voltage power supply to the desired voltage level.
According to a second aspect of the invention, the I/O pad line is configurably connected to the input reference voltage line driving the input reference voltage input port (hereinafter referred to as the xe2x80x9creference inputxe2x80x9d) in the IOB. Therefore, an I/O pad can be used to supply the input reference voltage.
According to a third aspect of the invention, the reference input of an IOB is configurably connected in the IOB to any of two or more available input reference voltages. Alternatively, the output voltage supply of an IOB is configurably connected in the IOB to any of two or more available output supply voltages.
According to a fourth aspect of the invention, a single input reference voltage is applied to each IOB, with the IOBs grouped into sets. Each set of IOBs has a separate input reference voltage. In one embodiment, each input reference voltage is applied to the IOBs on one half-edge of the FPGA die. Therefore, on a rectangular die, eight separate input reference voltages are applied. These input reference voltages can be connected together outside the FPGA package, or within the FPGA package by leads or other means, or configurably connected within the FPGA.
According to a fifth aspect of the invention, the IOBs are grouped into sets and each set of IOBs has a separate output voltage supply. In one embodiment, each output voltage supply is applied to the IOBs on one half-edge of the FPGA die. Therefore, on a rectangular die, eight separate output voltage supplies are applied to eight sets of IOBs. In one embodiment, input reference voltages and output voltage supplies are each applied to one half-edge of an FPGA die. Therefore, in this embodiment eight separate input reference voltages and eight separate output voltage supplies are applied to eight sets of IOBs.